Personal computers and work stations have as a main memory unit for storing data a DRAM (Dynamic Random Access Memory), onto which data can be recorded and retrieved.
The DRAM comprises a plurality of memory cells, each storing 1 bit of data. Each memory cell further comprises a MOS transistor and a capacitor. Data is stored in a memory cell as a potential appearing at the electrode of the capacitor. Data is stored in a memory cell by providing an H (high) or L (low) level to one of the electrodes of the capacitor through the MOS transistor. By putting the MOS transistor in a non-conductive state, the potential provided to the capacitor is held, and data is allowed to be stored therein. Since the memory cell of a DRAM has few elements, a DRAM with a large capacity can be produced at a relatively low cost.
Although the MOS transistor of the memory cell is put in a non-conductive state in order to sustain a potential in the capacitor, the potential held in the capacitor changes due to a sub-threshold leak current of the MOS transistor, inevitably data stored in the memory cell is lost. For this reason, periodical refresh operations are executed in the DRAM in order to maintain stored data. In this refresh operation, a potential, the polarity of which depends upon data stored in the memory cell, is again provided to the capacitor.
The 16Mbit DRAMs which are mass-produced at the present time have a refresh mode for implementing CBR (column address strobe before row address strobe, or CAS before RAS, or CBR) refresh operations. In this mode, a DRAM is provided with CBR timing with which, after a column-address strobe signal CAS has been lowered to the L level, a row-address strobe signal RAS is lowered. With CBR timing, a refresh address is generated in the DRAM and a refresh operation is carried out at the refresh address. The 16Mbit DRAM has two kinds of refresh cycles: 2K and 4K refresh cycles. Before the chip is put in a package in an assembly operation, a refresh-cycle type is set for the DRAM. That is, a DRAM chip is put in a package and shipped with a refresh-cycle type pre-selected. Thus, an operation to complete refreshing all memory cells in the DRAM with CBR timing applied to the DRAM 2K (2,048) times or 4K (4,096) times is pre-selected.
In Japanese Patent Laid-open No. Sho 59-167898, a DRAM having a mode called self refresh is disclosed. In the self-refresh mode, a refresh operation is automatically carried out when an external /RFSH clock signal provided to the chip is sustained at the L level for a duration of 15 to 16 seconds.
In the conventional DRAM described above, a refresh cycle of the self-refresh mode can not be selected from a plurality of refresh-cycle types. That is, DRAMs having different self-refresh cycles must be fabricated through distinct manufacturing lines with distinct masks, giving rise to a problem that the manufacturing cost is high.